preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.0.2.48a_bebz 1 33,554,432-bit (2,097,152 -word by 16-bit /4,194,304-word by 8-bit) cmos flash memory & 8,388,608-bit (524,288-word by 16-bit /1,048,576-word by 8-bit) cmos sram stacked- mcp (micro multi chip package) m6mgb/t331s8akt renesaslsis the m6mgb/t331s8akt is a stacked micro multi chip package (s- m mcp) that contents 32m-bit flash memory and 8m-bit static ram in a 52-pin tsop for lead free use. 32m-bit flash memory is a 4,194,304 bytes / 2,097,152 words, , single power supply and high performance non- volatile memory fabricated by cmos technology for the peripheral circuit and dinor (divided bit-line nor iv) architecture for the memory cell. all memory blocks are locked and can not be programmed or erased, when f-wp# is low. using software lock release function, program or erase operation can be executed. 8m-bit sram is a 1,048,576 bytes / 524,288 words asynchronous sram fabricated by cmos technology for the peripheral circuit . the m6mgb/t331s8akt is suitable for a high performance cellular phone and a mobile pc that are required to be small mounting area, weight and small power dissipation access time flash 70ns (max.) sram 85ns (max.) supply voltage vcc=2.7 ~ 3.0v ambient temperature ta=-40 ~ 85 c package 52pin tsop(type-ii), lead pitch 0.4mm outer-lead finishing:sn-cu application outline 52ptj-a mobile communication products description features pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 a15 a14 a13 a12 a11 a10 a9 a8 a19 s-ce1# f-rp# f-wp# s-ce2 a20 a18 a17 a7 a6 a5 a4 a3 s-ub# gnd s-lb# dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 f-vcc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# gnd 28 27 f-ce# a0 25 26 a2 a1 10.49mm s-vcc we# a16 du byte# 1 0 . 7 9 m m f-vcc s-vcc gnd a-1-a18 a19-a20 dq0-dq15 f-ce# s-ce1# s-ce2 oe# we# :vcc for flash :vcc for sram :gnd for flash/sram :flash/sram common address :address for flash :data i/o :flash chip enable :sram chip enable1 :sram chip enable2 :flash/sram output enable :flash/sram write enable f-wp# f-rp# byte# s-lb# s-ub# du :flashwrite protect :flash reset power down :flash/sram byte enable :sram lower byte :sram upper byte :do not use m6mgb/t331s8akt
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.0.2.48a_bebz 2 33,554,432-bit (2,097,152 -word by 16-bit /4,194,304-word by 8-bit) cmos flash memory & 8,388,608-bit (524,288-word by 16-bit /1,048,576-word by 8-bit) cmos sram stacked- mcp (micro multi chip package) m6mgb/t331s8akt renesaslsis capacitance mcp block diagram min.typ.max. cin input capacitance a20-a0, oe#, we#, f-ce#, f-wp#, f-rp#, s-ce1#, s-ce2, byte#, s-lb#, s-ub# 18 pf cout output capacitance dq15-dq0 22 pf symbol conditions ta=25 c, f=1mhz, vin=vout=0v unit limits parameter a0 to a20 a0 to a20 f-wp# f-rp# we# oe# s-ub# s-lb# 1) dq0 to dq15 32mbit dinor(iv) flash memory f-vcc gnd f-ce# 8mbit sram s-vcc a0 to a18 s-ce1# s-ce2 byte# 1) 2) 1) 2) 1) note 1): in case of x8 organization, a-1 is added, and only lower byte data(dq0 to dq7) are assigned toi/o and upper byte data(dq8 to dq15) are high-z. note 2): in the data sheet there are vcc s which mean f-vcc or "s-vcc". in the sram part there are ub# and lb# which mean s-ub# and s-lb# , respectively. note 3): du(don t use) pin must be open ,otherwise be inputted within 0v ~vcc.
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